Due to the increased density of modern integrated circuits (ICs), the amount of power consumed by modern ICs continues to escalate. In response, there has been an increasing focus to lower the power consumption of new digital hardware circuits. One approach to reducing power consumption is to employ so called clock gating, a technique which manufacturers have incorporated into the automated design of digital hardware circuits.
Clock gating is a well known technique used to reduce the power consumption of digital hardware circuits. It is often employed as one of several power saving techniques typically applied to synchronous circuits used in large microprocessors and other complex circuits. To save power, clock gating solutions add additional logic to a circuit to modify the functionality of the clock input of a flip-flop or latch, thereby disabling portions of the circuitry where flip-flops or latches do not change state.
Issues that arise with clock gating include both the cost of implementing the clock gating logic, the amount of power consumed by the clock gating logic portion of the circuit and the fact that applying clock gating techniques affects the timing of the clock signal. As a rule, the size of clock gating logic is proportional to the timing problems that accompany a clock gating implementation. One way to address this problem is to slow down the clock in order to allow gating function computations to finish without violating setup and hold times of the memory elements. This, however, is not usually a viable solution, and in fact, current synthesis tools reject logically valid clock gating solutions due to timing problems.
An alternative solution is to reduce the size of the clock gating logic portion of the circuit by approximation of the gating function. The main factor affecting the size of the logic is the number of inputs. By reducing the number of inputs, the size of the logic of the gate function is reduced, the preventing its rejection because of timing problems.
Therefore, there is a need for hardware development tool mechanism that can reduce the size of the logic necessary to implement clock gating in a digital design by over-approximating the clock gating function. Preferably, the development tool allows the use of clock gating techniques when the clock gating is applied to the critical path, by fixing the problem of time deficit simultaneously with calculating the clock gating function. In addition, any implementation of a proposed over-approximation of the original clock gating function must not slow the clock will decrease performance of the digital design.